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Jane Street revealed that its August ASIC puzzle contained a hardware checker for an 11-by-11 Star Battle puzzle. The company said it received about 400 submissions from more than 30 countries, with solvers using circuit tools, custom software and several different reverse-engineering approaches.
Jane Street has revealed that its ASIC puzzle concealed a hardware checker for an 11-by-11 Star Battle puzzle, after receiving about 400 submissions from more than 30 countries. The August challenge gave participants a chip’s final physical layout, without its netlist or internal signal names, and asked them to determine what it did.
In Star Battle, also called “Two Not Touch,” players must place exactly two stars in every row, column and colored region. Stars cannot touch, including diagonally. According to Jane Street’s explanation, the chip accepts 121 inputs over 121 cycles, one for each square, indicating whether a star is placed there.
The circuit checks row and column totals with 2-bit counters, maps squares to regions using a 121-bit ROM, and counts stars in each region. A delay line checks for adjacent stars, while a separate total-star counter supports Easter egg outputs. The individual checks feed into a combined success signal. Jane Street says the output strings are stored in ROM and obfuscated using a small LFSR driven by the board; on success, the circuit emits the solution string, “TWO STARS.”
Most incorrect boards produce “TRY AGAIN,” though the company says some inputs trigger Easter egg outputs. The chip was designed with the SKY130 open-source standard cell library and the LibreLane toolchain. Jane Street reports that submissions came from high school students, researchers, engineers and retirees. Solvers used tools including KLayout, Yosys and Z3, as well as custom programs written in languages such as Python, Rust, C++, OCaml, Haskell and Odin.
What the Chip Was Checking
The challenge turned a physical chip layout into a reverse-engineering problem: participants had to recover enough of the circuit’s behavior to identify its purpose and find an input board that passed its checks. The revealed design connects digital logic and puzzle rules, showing how counters, stored mappings and a delay line can implement the constraints of a grid puzzle.
The varied solutions also show that there was more than one route through the problem. Jane Street describes submissions that extracted a netlist from the layout, simulated the recovered circuit, traced logic backward from the success output, or probed how internal registers responded to test inputs. That range made the results a record of different technical approaches, not just a single answer.
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From Layout to Logic
The original challenge supplied the finished GDS layout, a file format used to represent chip geometry, but omitted the logical netlist and signal names. Jane Street says it retained standard cell names in the layout, allowing participants to use tools such as Magic and KLayout to help extract a gate-level netlist. Some participants instead wrote their own extraction software.
Recovering a circuit graph was only part of the task. Solvers also needed to model the cells and simulate the design. The supplied waveform provided an input sequence and expected outputs, but matching that trace alone did not prove a simulator was correct. Jane Street recounts one example in which a Python model reproduced the trace but mishandled tie-high cells, which should output a constant one. That error disabled the adjacency check in the model; comparison with an Icarus Verilog simulation on additional inputs exposed the problem.
“We supplied the physical layout, but not a netlist or internal signal names, and it was up to you to reverse-engineer the internals.”
— Jane Street, describing the challenge
hardware reverse engineering tools
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Limits of the Published Results
Jane Street’s account gives an approximate submission count and says entries came from more than 30 countries, but it does not report how many submissions found the intended board, how many were fully correct, or how entries were evaluated. The supplied source excerpt also ends during its discussion of participant writeups, so it does not include every method or result highlighted in the full post.
The source does not specify the year of the August puzzle release or the date the results post appeared. It also does not give the chip’s size, power use, or fabrication status. The account describes a design built with an open-source library and toolchain; it does not establish that a physical chip was manufactured.
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Further Solver Writeups
Jane Street’s results post points readers to participant writeups and examples of their extraction and simulation techniques. The source does not announce another puzzle or a later technical milestone. Readers seeking more detail can consult the linked original report and the solver accounts it references.
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Key Questions
What did the ASIC puzzle chip do?
It checked whether a sequence of 121 square inputs formed a valid 11-by-11 Star Battle board, with two stars in each row, column and region and no touching stars.
How did the chip indicate a correct board?
Jane Street says the checks were combined into a success signal. When the conditions passed, the output logic deobfuscated and emitted the string “TWO STARS.”
How many people submitted solutions?
Jane Street reports about 400 submissions from more than 30 countries. It does not state how many submissions solved the puzzle correctly.
What tools did solvers use?
The company names KLayout, Yosys and Z3, along with custom tools written in several programming languages. Some participants extracted a netlist from the layout; others focused on simulation or tracing the circuit’s logic.
Source: hn
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